The present invention relates to a method for evaluating the surface state of a semiconductor substrate during a fabrication process of semiconductor devices and to a method for controlling the fabrication process of semiconductor devices based on the results of evaluation.
An xe2x80x9cI-V methodxe2x80x9d is known as an exemplary technique for evaluating the surface state of a semiconductor substrate. In the I-V method, a metal electrode, which forms a Schottky barrier with a semiconductor substrate, is brought into contact with the substrate, and a voltage is applied between the substrate and the electrode to measure the amount of current flowing therebetween. Based on the resulting variation in current with the voltage applied, the surface state of the semiconductor substrate is evaluated according to this technique.
FIG. 18 is a schematic illustrating a measuring principle of this I-V method. As shown in FIG. 18, an Si substrate 1, which is a target of measurement, is placed on a stage 2 of this measuring system. And a mercury electrode 3, which forms a Schottky barrier with the Si substrate 1, is in contact with the surface of the Si substrate 1. A variable voltage is applied from a voltage supply 16 between the Si substrate 1 and the mercury electrode 3. And the resultant current and voltage are measured with an ammeter 17 and a voltmeter 5, respectively.
Hereinafter, results of I-V evaluation on the surface state of the semiconductor substrate 1, which was exposed to a plasma of the type increasing a contact resistance, will be described. In this case, an n-type silicon wafer, of which the surface is a (100) crystallographic plane and the resistivity is 10 xcexa9xc2x7cm, was used as the Si substrate 1. A parallel-plate reactive ion etching (RIE) system was used to form a region with plasma-induced damage (hereinafter, simply referred to as a xe2x80x9cdamaged layerxe2x80x9d). A mixed gas of CHF3 and O2 was used as an etching gas, the pressure of the gas was set at 5 Pa, and a radio frequency power of 1 kW was applied at 13.56 MHz. Under these conditions, a damaged layer was formed within the Si substrate 1, which was then subjected to an O2 down-flow plasma ashing process, and an organic compound deposited on the Si substrate 1 was removed therefrom. Subsequently, the Si substrate was subjected to down-flow etching within a plasma ambient using a mixed gas of CF4 and O2, thereby partially removing a surface region of the Si substrate 1 to a depth of 5 to 60 nm. During this down-flow etching (also called xe2x80x9cchemical dry etching (CDE)xe2x80x9d), the pressure of the gas was 133 Pa and an RF power of 300 W was applied at 13.56 MHz. With such CDE etching, since part of a semiconductor substrate is going to be removed by a chemical action almost without receiving the impact of plasma ions, no damaged layer is newly formed within the semiconductor substrate.
Thereafter, the Si substrate 1 was subjected to ashing with O2 plasma, cleaning with H2SO4 and H2O2 and cleaning with diluted HF. Then, using the arrangement shown in FIG. 18, a variable voltage was applied between the mercury electrode 3 and the Si substrate 1 to measure resulting current and voltage by the ammeter 17 and voltmeter 5, respectively.
FIG. 19 illustrates data on the current-voltage characteristics obtained by this measurement. In FIG. 19, a curve indicated by xe2x80x9ccontrolxe2x80x9d shows data on a bare silicon substrate 1, which was not subjected to either RIE or CDE. As shown in FIG. 19, in a substrate that was etched by the CDE technique to a depth as small as 5 nm, the resulting current was small and the current-voltage characteristics were disturbed. Accordingly, it is estimated that a lot of damage would have remained in such a substrate. It is also understood that some samples, which were supposed to show Schottky properties, actually show ohmic properties. Furthermore, even a bare silicon substrate showed ohmic properties if the substrate had been subjected to the CDE process. Thus, it is suggested that some change would have been caused in the surface state of the Si substrate as a result of the CDE process.
Next, supposing that any CDE-etched sample showed a similar variation in its surface state, RIE-induced damage in a CDE-etched sample was evaluated.
FIG. 20 illustrates a variation in current with an etch depth where a voltage applied is xe2x88x920.2 V in the I-V characteristic curves shown in FIG. 19, to show in detail how the damage recovers in a CDE-etched sample. As shown in FIG. 20, when the etch depth is 40 nm, the current abruptly increases. In other words, it can be understood that the damaged layer reaches a depth of 40 nm as measured from the surface of the Si substrate 1.
As can be understood from the foregoing description, the depth of a damaged layer, which has been formed within a plasma-processed Si substrate 1, can be known during the fabrication process by utilizing the conventional I-V method. Accordingly, even if no devices such as transistors have been formed yet on the Si substrate 1, the surface state of the Si substrate 1 can be evaluated almost non-destructively. And based on the results of evaluation, it can be determined whether or not the plasma processing conditions should be changed and whether or not the process should proceed to the next step.
The conventional I-V evaluating method, however, has the following drawbacks.
FIG. 5 illustrates a resulting variation in contact resistance with a CDE etch depth of an Si substrate, which had been examined in the above-described manner and on which an AlSiCu interconnect had been formed. As shown in FIG. 5, even in the damaged Si substrate, when the depth of the etched part of the substrate reaches 3 nm, the contact resistance has decreased drastically. And when the etch depth reaches 8 nm, the contact resistance is almost zero. In other words, the increase in contact resistance due to the damage can be eliminated on and after the etch depth reaches 8 nm as measured from the surface of the Si substrate according to the results shown in FIG. 5. But the results shown in FIG. 5 are contradictory to those of the conventional I-V evaluation shown in FIG. 20. According to the conventional I-V evaluation, damage can be detected with sufficiently high sensitivity. However, in accordance with the I-V evaluation, subtle defects, which are located much deeper than the damaged layer to be actually removed, are also detected unnecessarily. That is to say, although some of the damages, which are located at a depth of 40 nm as shown in FIG. 20, may have no impact on the performance of semiconductor devices, the conventional I-V evaluation defines the etch depth at 40 nm. As a result, overly excessive etching is performed unintentionally, because 40 nm is much deeper than an actually required depth of 8 nm.
Accordingly, in actuality, the results of conventional I-V evaluation on the depth of the damaged layer were not applicable in an xe2x80x9cin-linexe2x80x9d fashion (or between processing steps of a fabrication process) to the determination of an etch depth for the purpose of removing the damaged layer. Thus, in practice, the depth of the damaged layer to be removed was determined empirically by measuring a contact resistance after interconnection had been formed.
An object of the present invention is providing respective methods for examining a semiconductor substrate and controlling a fabrication process of semiconductor devices, which contribute to various determinations during the fabrication process, by taking measures to evaluate the surface state of a plasma-processed semiconductor substrate with no interconnects formed thereon.
To achieve this object, according to the present invention, the surface state of a semiconductor substrate is evaluated by analyzing an electrical phenomenon resulting from a trapping change in the interface between the substrate and a measuring terminal placed thereon. For example, either a variation in current with a constant voltage applied between the substrate and the terminal or a variation in voltage with a constant current supplied therebetween is detected according to the present invention.
A method for examining a semiconductor substrate according to the present invention includes the steps of: a) placing a measuring terminal on the semiconductor substrate; b) applying one of voltage and current as an electrical stress between the substrate and the terminal at a constant rate to measure a variation in the other electrical stress caused between the substrate and the terminal; and c) evaluating the surface state of the substrate based on the variation in the other electrical stress.
In accordance with this method, current is injected into the surface region of the semiconductor substrate. As a result, the trap centers within the damaged layer are filled with charges and the band state changes in the semiconductor substrate. In this case, the change in band state is determined depending on a defect density near the surface of the semiconductor substrate. Accordingly, based on a variation in voltage or current due to the change in band state, information about the defect density at a depth of several nanometers as measured from the surface of the semiconductor substrate can be obtained. As a result, evaluation can be carried out quantitatively based on an actual defect density.
In one embodiment of the present invention, such a combination of materials as forming a Schottky barrier therebetween may be selected in the step a) for the semiconductor substrate and the measuring terminal. In the step b), the electrical stress may be applied in such a direction as causing a forward current.
In such an embodiment, the measurement can be performed easily.
In another embodiment of the present invention, the steps a) through c) may be performed on an initial semiconductor substrate with a damaged layer formed within the surface thereof and on a processed semiconductor substrate, from which part of the damaged layer has been removed by a predetermined depth. It may be estimated how deep the damaged layer has been removed based on the variation in the other electrical stress between the initial and processed semiconductor substrates.
In such an embodiment, only the depth of a particular portion of the damaged layer, having impact on the performance of semiconductor devices, can be detected accurately. That is to say, unlike the conventional I-V evaluation, a non-negligible portion of the damaged layer, having impact on the performance of semiconductor device, can be distinguished from the other negligible portion of the damaged layer. Thus, this method is applicable to an in-line non-destructive test in practice.
In this particular embodiment, current may be supplied as the electrical stress in the step b) and a defect density N in a surface region of the semiconductor substrate may be obtained in the step c) based on a variation xcex94V in the voltage, which is the other electrical stress, with time. The variation xcex94V may be given by xcex94V=Xxc2x7qxc2x7N/∈, where X is a depth at which a charge trap center is located, q is a quantity of charges and ∈ is a relative dielectric constant of the semiconductor substrate.
In such an embodiment, the defect density N within the semiconductor substrate can be estimated based on the variation xcex94V in voltage. Thus, it is possible to spot where that portion of the damaged layer with a defect density high enough to seriously affect the performance of semiconductor devices is located within the semiconductor substrate.
In still another embodiment, the method may further include the step of forming an oxide film over the semiconductor substrate prior to the step a). In the step a), the measuring terminal may be placed on the oxide film formed over the semiconductor substrate.
In such an embodiment, the measuring sensitivity can be improved.
In this particular embodiment, the oxide film may be formed at a temperature as low as 400xc2x0 C. or less in the step of forming the oxide film.
In such an embodiment, the crystallinity in the region to be measured does not recover at such a low temperature. Accordingly, the accuracy of measurement does not decline.
In an alternate embodiment, the oxide film may be formed to have such a thickness as enabling charge tunneling in the step of forming the oxide film.
In such an embodiment, it is possible to prevent the oxide film from interfering with the current flow, thus maintaining satisfactory measuring sensitivity.
In the embodiment where the oxide film is formed, the steps a) through c) may also be performed on an initial semiconductor substrate with a damaged layer formed within the surface thereof and on a processed semiconductor substrate, from which part of the damaged layer has been removed by a predetermined depth. And it may be estimated how deep the damaged layer has been removed based on the variation in the other electrical stress between the initial and processed semiconductor substrates.
In such an embodiment, the same effects as those described above can also be attained.
In this particular embodiment, current may be supplied as the electrical stress in the step b). And a depth, at which a variation in saturation value of the voltage, or the other electrical stress, reaches its local maximum, may be estimated as the depth of the damaged layer in the step c).
In such an embodiment, if several local maximums are obtained, then the respective types of impurities bringing about these local maximums can be known. Accordingly, a depth, which is reached by an impurity affecting the performance of semiconductor devices, can also be known. Thus, based on these results of evaluation, it is possible to etch the substrate to the very depth of the damaged layer, which is a root of problems in practice, and thereby avoid excessive etching.
The present invention also provides a method for controlling a fabrication process of semiconductor devices. In this method, the fabrication process is supposed to include the steps of: i) processing a semiconductor substrate under such conditions as doing damage to the substrate; and ii) removing a damaged layer, which has been caused by the step i). The process control method includes the steps of: a) placing a measuring terminal on the substrate at an arbitrary point in time during the steps i) and ii); b) applying one of voltage and current as an electrical stress between the substrate and the terminal at a constant rate to measure a variation in the other electrical stress caused between the substrate and the terminal; c) evaluating the surface state of the substrate based on the variation in the other electrical stress; and d) controlling the step ii) based on results of evaluation in the step c).
In accordance with this process control method, it is possible to control the process step of removing a plasma-etch-induced damaged layer, for example, to an adequate depth by utilizing the inventive method for examining a semiconductor substrate.
In one embodiment of the present invention, conditions for the step ii) may be changed or an endpoint of the step ii) may be detected in the step d).
In another embodiment of the present invention, such a combination of materials as forming a Schottky barrier therebetween may be selected in the step a) for the semiconductor substrate and the measuring terminal. And in the step b), the electrical stress may be applied in such a direction as causing a forward current.
Alternatively, the process control method may further include the step of forming an oxide film over the semiconductor substrate prior to the step a), in which the measuring terminal may be placed on the oxide film formed over the substrate.
In still another embodiment, the steps a) through c) may be performed on an initial semiconductor substrate with a damaged layer formed within the surface thereof and on a processed semiconductor substrate, from which part of the damaged layer has been removed by a predetermined depth. And in the step d), the step ii) may be controlled based on the variation in the other electrical stress between the initial and processed semiconductor substrates.
In this particular embodiment, if a Schottky contact is used, current may be supplied as the electrical stress in the step b). In the step c), a defect density N in a surface region of the semiconductor substrate may be obtained based on a variation xcex94V in the voltage with time. The variation xcex94V is given by xcex94V=Xxc2x7qxc2x7N/∈, where X is a depth at which a charge trap center is located, q is a quantity of charges and ∈ is a relative dielectric constant of the semiconductor substrate. And in the step d), when a variation in the defect density N between the initial and processed semiconductor substrates reaches a predetermined value, it is determined that the step ii) is finished.
Alternatively, according to a method using an oxide film as an interposed film, current may be supplied in the step b) as the electrical stress. And in the step c), a depth, at which a variation in saturation value of the voltage, or the other electrical stress, reaches its local maximum, may be estimated as the depth of the damaged layer.